{"id":1532,"date":"2018-07-30T13:04:31","date_gmt":"2018-07-30T13:04:31","guid":{"rendered":"http:\/\/centruldecalcul.ro\/astr\/?p=1532"},"modified":"2018-08-31T07:10:10","modified_gmt":"2018-08-31T07:10:10","slug":"fundamente-ale-arhitecturii-microprocesoarelor","status":"publish","type":"post","link":"https:\/\/old.astr.ro\/en\/fundamente-ale-arhitecturii-microprocesoarelor\/","title":{"rendered":"Fundamente ale arhitecturii microprocesoarelor"},"content":{"rendered":"<img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-1533 alignleft\" src=\"\/wp-content\/uploads\/2018\/07\/4864_39_poza_1-300x300.jpg\" alt=\"\" width=\"300\" height=\"300\" srcset=\"https:\/\/old.astr.ro\/wp-content\/uploads\/2018\/07\/4864_39_poza_1-300x300.jpg 300w, https:\/\/old.astr.ro\/wp-content\/uploads\/2018\/07\/4864_39_poza_1-150x150.jpg 150w, https:\/\/old.astr.ro\/wp-content\/uploads\/2018\/07\/4864_39_poza_1-420x420.jpg 420w, https:\/\/old.astr.ro\/wp-content\/uploads\/2018\/07\/4864_39_poza_1.jpg 550w\" sizes=\"auto, (max-width: 300px) 100vw, 300px\" \/>\r\n<p style=\"font-weight: 400;\">A ap\u0103rut cartea\u00a0<em>Fundamente ale arhitecturii microprocesoarelor<\/em><b><strong>,\u00a0<\/strong><\/b>autor prof.univ.dr.ing.<b><strong>\u00a0<\/strong><\/b><b><strong><a href=\"https:\/\/work.astr.ro\/membri\/vintan-lucian-nicolae_181\">VIN\u0162AN N. LUCIAN<\/a>,<\/strong><\/b>\u00a0Editura Matrix Rom, Bucure\u015fti, ISBN\u00a0978-606-25-0276-8, 2016 (547 pg.)<\/p>\r\n<p style=\"font-weight: 400;\"><a href=\"http:\/\/www.matrixrom.ro\/romanian\/editura\/domenii\/cuprins.php?cuprins=FA50\">http:\/\/www.matrixrom.ro\/romanian\/editura\/domenii\/cuprins.php?cuprins=FA50<\/a><\/p>\r\n<p style=\"font-weight: 400;\"><b><strong>PREFA\u021a\u0102<\/strong><\/b><\/p>\r\n<p style=\"font-weight: 400;\">Scopul principal al acestei c\u0103r\u021bi este acela de a familiariza cititorul cu anumite aspecte, considerate mai importante \u0219i, de asemenea, mai pu\u021bin perisabile, referitoare la arhitectura microprocesoarelor de azi \u0219i, eventual, chiar de m\u00e2ine. A\u0219adar, cartea de fa\u021b\u0103 are un preponderent caracter formativ, focaliz\u00e2ndu-se pe prezentarea unor cuno\u0219tin\u021be generice, fundamentale, oarecum independente de implement\u0103ri particulare, comerciale. Totu\u0219i, bazat pe propria experien\u021b\u0103 de predare [Vin15b], dar \u0219i de cercetare \u0219tiin\u021bific\u0103 a autorului \u00een domeniul arhitecturilor de calcul, credem c\u0103 prezentarea este una original\u0103, reflect\u00e2nd o medita\u021bie \u0219i un efort de \u00een\u021belegere relativ \u00eendelungate asupra subiectelor tratate, situate la nivelul interfe\u021bei\u00a0<em>hardware-software<\/em>. Pentru fiecare metod\u0103 sau tehnic\u0103 prezentat\u0103 s-a \u00eencercat revelarea metaforei cognitive care st\u0103 la baza acesteia, \u00een speran\u021ba c\u0103, astfel, cuno\u0219tin\u021bele se vor consolida. Uneori, anumite contribu\u021bii originale ale autorului \u00een domeniul sistemelor de calcul, sau ale unor cercet\u0103tori consacra\u021bi, publicate \u00een reviste \u0219i \u00een conferin\u021be interna\u021bionale de un bun nivel \u0219tiin\u021bific, sunt integrate \u00een prezentare, \u201ctopite\u201d \u00eentr-o form\u0103 mai accesibil\u0103 (spre exemplu, prezentarea fundamentelor predic\u021biei dinamice neuronale a instruc\u021biunilor de salt condi\u021bionat, idee introdus\u0103 \u00een premier\u0103 de autor, la nivel mondial, prin publicarea unui articol la conferin\u021ba\u00a0<em>International Joint Conference on Neural Networks, Washington DC, USA, 10-16 July, 1999<\/em>). Consider\u0103m c\u0103 integrarea unor contribu\u021bii \u0219tiin\u021bifice ale autorului, sau familiare acestuia, constituie un demers binevenit \u00eentr-un tratat universitar, contribuind la o viziune specific\u0103 util\u0103, la puncte de vedere care pot st\u00e2rni interesul, curiozitatea \u0219i chiar dezacordul (!) cititorului. Credem c\u0103 este nevoie de asemenea c\u0103r\u021bi, care nu intr\u0103 \u2013 pentru c\u0103 nici nu ar putea-o face \u2013 \u00een concuren\u021b\u0103 cu marile\u00a0<em>text-book<\/em>-uri ale domeniului (unele citate \u00een bibliografie), ci, dimpotriv\u0103, prezint\u0103 domeniul \u00eentr-un mod mult mai succint \u0219i insist\u00e2nd pe tematicile mai familiare autorului, printr-o experien\u021b\u0103 de cercetare \u0219tiin\u021bific\u0103 proprie.<\/p>\r\n<p style=\"font-weight: 400;\">Acest tratat universitar reutilizeaz\u0103 \u0219i integreaz\u0103 \u00eentr-un tot unitar, sub o form\u0103 \u00eembun\u0103t\u0103\u021bit\u0103 \u0219i extins\u0103 \u00eentr-un mod semnificativ, p\u0103r\u021bi ale unor lucr\u0103ri anterioare, scrise \u0219i publicate de autor sub forma unor monografii sau articole tehnico-\u0219tiin\u021bifice. Autorul a rescris \u0219i a actualizat anumite p\u0103r\u021bi ale acestor lucr\u0103ri, care abordau chestiuni esen\u021biale referitoare la arhitectura sistemelor de calcul, revizuindu-le, sintetiz\u00e2ndu-le \u0219i \u00eembog\u0103\u021bindu-le \u00een cartea de fa\u021b\u0103, \u00een speran\u021ba c\u0103 sub aceast\u0103 form\u0103 nou\u0103, poate mai didactic\u0103 dec\u00e2t versiunile anterioare, informa\u021bia prezentat\u0103 va fi mai u\u0219or asimilabil\u0103 de c\u0103tre studen\u021bii \u0219i speciali\u0219tii interesa\u021bi. S-au utilizat \u00een acest scop, \u00een principal, lucr\u0103rile VIN\u0162AN N. LUCIAN \u2013\u00a0<em>Arhitecturi de procesoare cu paralelism la nivelul instruc\u021biunilor<\/em>, Editura Academiei Rom\u00e2ne, Bucure\u015fti, 2000; VIN\u0162AN N. LUCIAN \u2013\u00a0<em>Prediction Techniques in Advanced Computing Architectures<\/em>\u00a0(\u00een limba englez\u0103), Matrix Rom Publishing House, Bucharest, 2007; VIN\u0162AN N. LUCIAN, FLOREA ADRIAN \u2013\u00a0<em>Microarhitecturi de procesare a informa\u0163iei<\/em>, Editura Tehnic\u0103, Bucure\u015fti, 2000; FLOREA ADRIAN, VIN\u0162AN N. LUCIAN \u2013\u00a0<em>Simularea \u015fi optimizarea arhitecturilor de calcul \u00een aplica\u0163ii practice<\/em>, Editura Matrix Rom, Bucure\u015fti, 2003, dar \u0219i altele, importante, ale autorului sau ale altora, precum anumite\u00a0<em>text-book<\/em>-uri de notorietate \u0219i apreciere mondiale \u00een domeniul sistemelor de calcul (v. bibliografia c\u0103r\u021bii). A\u0219adar, textele preluate din propriile lucr\u0103ri ale autorului au fost rescrise, cu modific\u0103ri \u0219i ad\u0103ugiri semnificative \u0219i structurate aici sub forma unei c\u0103r\u021bi de sine st\u0103t\u0103toare, care\u00a0\u201ccurge\u201d natural, de la simplu la complex \u0219i care, sper\u0103 autorul, d\u0103 seama asupra unor aspecte tehnico-\u0219tiin\u021bifice fundamentale ale microprocesoarelor de uz general, ale modului \u00een care acestea proceseaz\u0103 programele. \u00cen ciuda caracterului preponderent formativ, la nivel universitar, consider\u0103m c\u0103 o parte important\u0103 a acestei lucr\u0103ri con\u021bine informa\u021bii \u0219i cuno\u0219tin\u021be izvor\u00e2te dintr-o experien\u021b\u0103 vie a autorului \u00een acest domeniu, at\u00e2t pe plan didactic, c\u00e2t \u0219i \u0219tiin\u021bific, care ar putea trezi curiozitatea speciali\u0219tilor. Spre exemplu, \u00een acest sens, arhitectura sistemelor de calcul este prezentat\u0103, \u00een premier\u0103 \u00eentr-un curs universitar credem noi, \u00eentr-o str\u00e2ns\u0103 leg\u0103tur\u0103 cu anumite metode de \u00eenv\u0103\u021bare automat\u0103 (<em>machine learning<\/em>, de tip re\u021bele neuronale, algoritmi genetici etc.) dar \u0219i cu anumite metode matematice, deosebit de utile \u00een analiza unor modele de procesare (algebre logice de tip\u00a0<em>fuzzy<\/em>, metode euristice de optimizare multi-obiectiv, teoria informa\u021biei etc.) Aceasta exprim\u0103, de fapt, viziunea interdisciplinar\u0103 a autorului, dezvoltat\u0103 \u0219i prin activitatea sa \u0219tiin\u021bific\u0103 de mai bine de 25 de ani, prin care \u00eencearc\u0103 s\u0103 contribuie, dup\u0103 modestele sale puteri, la maturizarea empiricei discipline inginere\u0219ti numite \u201carhitectura sistemelor de calcul\u201d, prin utilizarea \u0219i adaptarea unor metode teoretice mai riguroase. Printre lucr\u0103rile de pionierat \u00een acest sens au fost \u0219i cele semnate de autor, fertile prin multiple cit\u0103ri independente, anume\u00a0<em>STEVEN G.,\u00a0<b><strong>VIN\u021aAN L.<\/strong><\/b>\u00a0&#8211; Modelling Superscalar Pipelines with Finite State Machines, &#8222;Proceedings of the 22<sup>nd<\/sup>\u00a0Euromicro\u201996 Conference. Beyond 2000: Hardware\/Software Design Strategies&#8221;, September\u00a0<b><strong>1996<\/strong><\/b>, Prague, Czech Republic, pp. 20-25, IEEE Computer Society Press, Los Alamitos, California, USA, ISBN 0-8186-7703-1, Library of Congress Number 96-79894\u00a0<\/em>respectiv\u00a0<b><strong><em>VIN\u021aAN L.<\/em><\/strong><\/b><em>\u00a0&#8211; Towards a High Performance Neural Branch Predictor, Proceedings of The International Joint Conference on Neural Networks &#8211; IJCNN \u201999 (CD-ROM, ISBN 0-7803-5532-6), pp. 868 \u2013 873, vol. 2, Washington DC, USA, 10-16 July,\u00a0<b><strong>1999\u00a0<\/strong><\/b><\/em>(aceast\u0103 a 2-a lucrare a introdus, \u00een premier\u0103, conceptul de predictor dinamic neuronal \u00een arhitectura calculatoarelor, av\u00e2nd 57 de cit\u0103ri independente p\u00e2n\u0103 \u00een anul 2015.) \u00centr-adev\u0103r, arhitectura sistemelor de calcul este \u00eenc\u0103 o \u0219tiin\u021b\u0103 inginereasc\u0103 preponderent empiric\u0103, insuficient de matur\u0103 din punct de vedere teoretic, bazat\u0103 \u00een principal pe metode de\u00a0<em>benchmarking<\/em>. Dezvoltarea sa a fost una predominant conjunctural\u0103, generat\u0103 deseori de limit\u0103ri tehnologice particulare, lipsindu-i un cadru de dezvoltare riguros, matematizat, \u00eenc\u0103 de la \u00eenceputuri. Astfel, ideile novatoare ale domeniului au ap\u0103rut, deseori, f\u0103r\u0103 a se con\u0219tientiza suportul lor teoretic mai ad\u00e2nc, deseori comun. Spre exemplu, ideea de memorie virtual\u0103 apare implementat\u0103 prin anul 1962, \u00eenaintea celei de memorie cache (1965). \u00cen\u021belegerea faptului c\u0103, \u00een esen\u021b\u0103, sunt idei cu o baz\u0103 comun\u0103 din punct de vedere teoretic (al teoriei statistice a probabilit\u0103\u021bilor), a ap\u0103rut ulterior. Un alt exemplu: predictoarele dinamice aferente instruc\u021biunilor de salt condi\u021bionat s-au dezvoltat f\u0103r\u0103 ca inventatorii lor s\u0103 \u00een\u021beleg\u0103 c\u0103 acestea sunt, de fapt, predictoare stohastice de tip\u00a0<em>Markov<\/em>. Abia \u00een anul 1996, dr.\u00a0<em>Trevor Mudge<\/em>\u00a0\u00een\u021belege acest fapt \u0219i public\u0103 un articol l\u0103muritor, dar, din p\u0103cate, cu efecte\u00a0 limitate asupra domeniului. \u00cen fine, un alt exemplu: procesarea vectorial\u0103 nu este prezentat\u0103 \u00een literatura de specialitate \u00een contextul conceptului natural, mai general, de spa\u021biu vectorial. Con\u0219tientizarea faptului c\u0103 procesarea vectorial\u0103 are ca baz\u0103 teoretic\u0103 no\u021biunea fertil\u0103 de spa\u021biu vectorial euclidian normat, ar putea avea nu doar un beneficiu cognitiv, ci \u0219i unul utilitar, concret. \u00cen baza acestei con\u0219tientiz\u0103ri s-ar putea dezvolta, spre exemplu, procesoare cu facilit\u0103\u021bi hardware de evaluare a similarit\u0103\u021bii a doi vectori, pe baza unor norme matematice, care ar putea accelera semnificativ aplica\u021bii de tip clasificare\/clustering. \u0218i ast\u0103zi remarc\u0103m o dezvoltare oarecum dezordonat\u0103, conjunctural\u0103, a domeniului (a se vedea, spre exemplu, dezvoltarea\u00a0<em>ad-hoc<\/em>\u00a0a sistemelor\u00a0<em>multicore<\/em>\u00a0din ultimii ani, precum \u0219i cea a limbajelor de programare concurente, prin intermediul c\u0103rora acestea s\u0103 fie exploatate corespunz\u0103tor.) O mare problem\u0103 teoretic\u0103 a domeniului arhitecturilor de calcul const\u0103 \u00een faptul c\u0103 cercet\u0103rile, \u00een marea lor majoritate bazate pe\u00a0<em>benchmarking<\/em>, dup\u0103 cum am mai men\u021bionat, nu sunt reproductibile sau sunt extrem de dificil (laborios) reproductibile. Complexitatea domeniului, legat\u0103 \u00een principal de procesarea unor programe obiect de mari dimensiuni \u0219i care \u0219i-au pierdut semantica \u00een urma compil\u0103rii, este departe de a fi st\u0103p\u00e2nit\u0103 \u00een mod corespunz\u0103tor. Metodologiile de cercetare \u0219i de evaluare a performan\u021belor sunt \u00eenc\u0103 relativ empirice. De aceea, credem c\u0103 orice efort de a \u201ematematiza\u201d aceast\u0103 \u0219tiin\u021b\u0103 predominant empiric\u0103, merit\u0103 subliniat.<\/p>\r\n<p style=\"font-weight: 400;\"><b><strong>\u00cen ciuda caracterului preponderent formativ al acestei c\u0103r\u021bi, ea \u00eencearc\u0103 s\u0103 sugereze cititorului \u0219i anumite idei \u0219tiin\u021bifice, unele, poate, chiar novatoare.<\/strong><\/b>\u00a0De altfel, la nivelul unui tratat sau curs universitar, amprenta \u0219tiin\u021bific\u0103 sau de interpretare original\u0103 a autorului sunt nu doar binevenite ci, credem noi, chiar necesare. (\u00cen caz contrar, am preda cu to\u021bii, 100% dup\u0103\u00a0<em>text-book<\/em>-urile clasice, \u00eentr-o uniformizare p\u0103guboas\u0103, care nu este specific\u0103 universit\u0103\u021bilor autentice.) Astfel,\u00a0<b><strong>un mesaj esen\u021bial al acestei c\u0103r\u021bi este acela c\u0103, domeniul numit\u00a0<em>Computer Architecture<\/em>\u00a0constituie, de fapt, un set uria\u0219 de studii de caz pentru cercet\u0103ri \u0219tiin\u021bifice autentice, mature, pe o baz\u0103 matematic\u0103 rafinat\u0103. Mai mult, domeniul empirico-ingineresc al arhitecturii sistemelor de calcul poate induce \u0219i motiva cercet\u0103ri \u0219tiin\u021bifice mai generale, cu adev\u0103rat profunde.<\/strong><\/b>\u00a0Pentru asta \u00eens\u0103, este nevoie de o generalizare a problemei particulare, tratate \u00een acest context pur ingineresc. Iat\u0103 doar c\u00e2teva asemenea probleme deschise, poten\u021bial fertile, cel pu\u021bin \u00een opinia autorului, prezentate \u00een carte \u00een mod natural \u0219i izvor\u00e2te din chiar propria sa experien\u021b\u0103 de cercetare:<\/p>\r\n\r\n<ul>\r\n \t<li style=\"font-weight: 400;\">Care este leg\u0103tura dintre complexitatea programelor dinamice deterministe \u0219i comportamentul lor, uneori impredictibil, entropic, cvasi-aleator?<\/li>\r\n \t<li style=\"font-weight: 400;\">Utilizarea cuno\u0219tin\u021belor de domeniu \u00een optimizarea multi-obiectiv a sistemelor de calcul, ridic\u0103 probleme \u0219tiin\u021bifice serioase, legate de reprezentarea adecvat\u0103 a cunoa\u0219terii de domeniu. Cum se poate reprezenta \u00een mod eficient cunoa\u0219terea din domeniul sistemelor de calcul, \u00een vederea optimiz\u0103rii eficiente a acestora? Cum poate fi integrat\u0103 aceast\u0103 cunoa\u0219tere specific\u0103, \u00een algoritmii generali de optimizare (\u00een general, euristici)?<\/li>\r\n \t<li style=\"font-weight: 400;\">Reprezentarea cunoa\u0219terii de domeniu, prin reguli logice de tip fuzzy, prezentat\u0103 \u00een lucrare (la finele Capitolului 4), conduce la problema deschis\u0103 a determin\u0103rii gradului de contradic\u021bie intrinsec, aferent unei astfel de micro-ontologii de domeniu, implic\u00e2nd probleme conexe importante (spre exemplu, dac\u0103 acest grad de contradic\u021bie este prea mare, ce se poate face? Eliminarea unor reguli? Care?) Generaliz\u0103ri ale problemei, \u00een contextul unor ontologii mai generale (ca semantic\u0103, dar \u0219i ca mod de reprezentare), ar putea fi de mare interes, at\u00e2t pe plan cognitiv, c\u00e2t \u0219i utilitar (spre exemplu, stabilirea gradului de contradic\u021bie existent \u00eentr-un text scris \u00een limbaj natural).<\/li>\r\n \t<li style=\"font-weight: 400;\">Ce ar putea deveni paradigma de optimizare multi-obiectiv de tip Pareto, \u00eentr-o abordare a mul\u021bimilor (fronturilor) Pareto \u00een paradigma teoriei fuzzy a mul\u021bimilor? (Adic\u0103, s\u0103 se determine gradul de apartenen\u021b\u0103 la frontul Pareto al fiec\u0103rui individ care apar\u021bine acestuia, pe baza gradului mutual de dominan\u021b\u0103. \u00cen toate abord\u0103rile actuale, un individ poate doar s\u0103 apar\u021bin\u0103, sau nu, frontului Pareto.)<\/li>\r\n \t<li style=\"font-weight: 400;\">Abord\u0103rile meta-algoritmice, de genul meta-predic\u021biilor, meta-clasific\u0103rilor, meta-optimiz\u0103rilor etc., prezentate \u00een aceast\u0103 carte strict \u00een contextul arhitecturii calculatoarelor, induc \u00een mod natural no\u021biunea de sinergie. (Altfel, meta-algoritmica sau abord\u0103rile hibride n-ar mai prea avea sens.) Cum s-ar putea ajunge la o teorie matematic\u0103 riguroas\u0103 a no\u021biunii de sinergie, \u00een context meta-algoritmic? Care este leg\u0103tura \u00eentre sinergia aceasta \u0219i sistemele neliniare din ingineria sistemelor? Etc.<\/li>\r\n<\/ul>\r\n<p style=\"font-weight: 400;\">Consider\u0103m asemenea probleme deschise ca fiind poten\u021bial fertile. Rezolvarea lor (aspectul cognitiv deci) ar putea conduce la solu\u021bionarea multor probleme utilitare derivate. Pe de alt\u0103 parte, asemenea abord\u0103ri interdisciplinare dezv\u0103luie o perspectiv\u0103 mai profund\u0103 a acestei discipline, considerat\u0103 preponderent empiric\u0103,\u00a0<b><strong>cu utilitate mult\u0103<\/strong><\/b>\u00a0(dat\u0103, \u00een fond, de toate dispozitivele electronice digitale de calcul pe care le folosim),\u00a0<b><strong>dar implic\u00e2nd cunoa\u0219tere \u0219tiin\u021bific\u0103 relativ pu\u021bin\u0103.<\/strong><\/b>\u00a0Credem c\u0103 situa\u021bia este similar\u0103 pentru multe alte discipline din domeniul mai larg al ingineriei sistemelor de calcul.<\/p>\r\n<p style=\"font-weight: 400;\">Pe scurt, lucrarea este structurat\u0103 astfel. Debutul se face cu o prezentare a istoriei sistemelor electronice de calcul numeric, insist\u00e2ndu-se nu doar pe geneza \u0219i evolu\u021bia ideilor tehnico-\u0219tiin\u021bifice, dar \u0219i pe oamenii care le-au dezvoltat. Apoi, se face o prezentare sintetic\u0103 a structurii \u0219i func\u021bion\u0103rii unui microsistem generic de calcul, insist\u00e2ndu-se asupra aspectelor fundamentale (microprocesor, memorii, interfe\u021be de I\/O, procesarea instruc\u021biunilor, moduri de lucru \u00eentre microprocesor \u0219i dispozitivele periferice etc.) Capitolul 2 prezint\u0103 arhitectura sub-sistemului de memorie al unui sistem de calcul. Se arat\u0103 c\u0103 \u00eentre viteza microprocesorului (de ordinul sutelor de picosecunde \u00een cazul celor mai avansate) \u0219i timpul de r\u0103spuns al memoriei principale (de ordinul zecilor de nanosecunde), respectiv al celei secundare (de ordinul c\u00e2torva milisecunde), exist\u0103 o \u201cpr\u0103pastie semantic\u0103\u201d. \u00cen consecin\u021b\u0103, se prezint\u0103 caracteristicile principale ale ierarhiei de memorii cache, dar \u0219i mecanismul de memorie virtual\u0103. \u00cenainte de aceste detalii \u00eens\u0103, autorul prezint\u0103 necesitatea acestor solu\u021bii, problema propriu-zis\u0103, care, deseori este mai important\u0103 chiar dec\u00e2t unele solu\u021bii particulare. De altfel, acest mod de prezentare, care starteaz\u0103 cu prezentarea c\u00e2t mai clar\u0103 a problemei puse \u00een discu\u021bie, a importan\u021bei acesteia, reprezint\u0103 un invariant al lucr\u0103rii (credem c\u0103 multe cursuri universitare p\u0103c\u0103tuiesc prin prezentarea unor solu\u021bii excesiv de complicate, f\u0103r\u0103 o precizare clar\u0103 a problemelor aferente acestora \u0219i a importan\u021bei acestor probleme \u00een contextul dat; plastic spus, \u201cde\u021bin solu\u021bie complicat\u0103, caut problema corespunz\u0103toare!\u201c). \u00cen capitolul urm\u0103tor se prezint\u0103 fundamentele microprocesoarelor RISC scalare, cu procesare\u00a0<em>pipeline<\/em>\u00a0a instruc\u021biunilor. Se insist\u0103 aici, \u00een mod clasic, pe problemele hazardurilor \u00een structurile pipeline de procesare a instruc\u021biunilor \u0219i, \u00een consecin\u021b\u0103, pe schi\u021barea principalelor solu\u021bii propuse \u00een literatura de specialitate. De asemenea, se prezint\u0103 aspecte importante legate de problematica excep\u021biilor \u00een procesoarele\u00a0<em>pipeline<\/em>, analiza alias-urilor de memorie (<em>memory disambiguation<\/em>), execu\u021bia predicativ-speculativ\u0103 (<em>sic!<\/em>) a instruc\u021biunilor etc. Capitolul 4 generalizeaz\u0103 abordarea celui precedent, referindu-se, \u00een principal, la microprocesoarele cu paralelism la nivelul instruc\u021biunilor, dar \u0219i la alte tipuri de sisteme de calcul mai avansate (spre exemplu, sisteme predictiv-speculative,\u00a0<em>multithreading<\/em>,\u00a0<em>multicore<\/em>\u00a0etc.) Se analizeaz\u0103 at\u00e2t abord\u0103rile hardware (algoritmul lui Tomasulo, bufferul de reordonare etc.) c\u00e2t \u0219i cele software (<em>scheduling<\/em>static al programului obiect) care urm\u0103resc acest scop (<em>Instruction Level Parallelism<\/em>), inclusiv pe baza unor studii de caz. Tot aici, se prezint\u0103 ideile principale care stau la baza microprocesoarelor cu proces\u0103ri multifir, arhitecturile de calcul vectorial (SIMD), care exploateaz\u0103 paralelismul la nivelul datelor, dar \u0219i c\u00e2teva elemente fundamentale referitoare la sistemele paralele de tip multiprocesor (<em>multicore,<\/em>MIMD). De asemenea, se prezint\u0103 \u00een premier\u0103 \u00een literatura tehnic\u0103 rom\u00e2neasc\u0103, cel pu\u021bin dup\u0103 \u0219tiin\u021ba autorului, un paragraf focalizat pe c\u00e2teva metode euristice de optimizare automat\u0103, de tip multi-obiectiv, aplicate sistemelor de calcul complexe. Acestea sunt augmentate prin utilizarea unor cuno\u0219tin\u021be din domeniul arhitecturii procesoarelor, exprimate prin logici de tip fuzzy, care le fac mai eficiente, dar \u0219i mai performante. Pe baza experien\u021bei de cercetare \u0219tiin\u021bific\u0103 a autorului, se face aici inclusiv o introducere \u00een problematica meta-optimiz\u0103rii sistemelor de calcul, const\u00e2nd \u00een utilizarea concurent\u0103 a mai multor algoritmi de optimizare, cu beneficii sinergice. Se continu\u0103 cu probleme propuse spre rezolvare, care provoac\u0103 cititorul s\u0103 aplice \u00een mod practic-aplicativ, cuno\u0219tin\u021bele expuse \u00een carte. Rezolvarea de aplica\u021bii practice este esen\u021bial\u0103 \u00een procesul de \u00eenv\u0103\u021bare (\u0219i) al acestui domeniu. Lucrarea se \u00eencheie cu o bibliografie selectiv\u0103 \u0219i cu un glosar, \u00een care se \u00eencearc\u0103 explicarea sintetic\u0103 a principalilor termeni tehnici utiliza\u021bi \u00een carte (deseori ace\u0219ti termeni, prelua\u021bi din limba englez\u0103, nu mai necesit\u0103 traduceri \u00een limba rom\u00e2n\u0103, intr\u00e2nd \u00een vocabularul tehnic al speciali\u0219tilor sub forma originar\u0103.) \u00cen mod deliberat, autorul a explicitat \u00een mod redundant anumite concepte, d\u00e2nd deseori formul\u0103ri echivalente alternative, utilizate \u00een literatura de specialitate, \u00een virtutea anticului principiu pedagogic care afirm\u0103 c\u0103\u00a0<em>repetitio (est) mater studiorum<\/em>.<\/p>\r\n<p style=\"font-weight: 400;\">Pentru cititorul care urm\u0103re\u0219te strict \u00eensu\u0219irea unor aspecte pur formative ale arhitecturii microprocesoarelor de uz general, f\u0103r\u0103 a fi deci preocupat momentan de probleme mai avansate, recomand\u0103m urm\u0103torul traseu de parcurgere a c\u0103r\u021bii:<\/p>\r\n\r\n<ul>\r\n \t<li style=\"font-weight: 400;\">Capitolul 1- integral (O introducere \u00een filosofia microsistemelor de calcul)<\/li>\r\n \t<li style=\"font-weight: 400;\">Capitolul 2 \u2013 integral (Memorii<em>cache<\/em>\u0219i memoria virtual\u0103)<\/li>\r\n \t<li style=\"font-weight: 400;\">Capitolul 3 (Microprocesoare<em>pipeline<\/em>scalare de tip\u00a0<em>RISC<\/em>), f\u0103r\u0103 sub-paragrafele intitulate \u201cProblema salturilor condi\u0163ionate impredictibile\u201d \u0219i \u201eFundamentele predic\u021biei neuronale a\u00a0<em>branch<\/em>-urilor\u201d<\/li>\r\n \t<li style=\"font-weight: 400;\">Capitolul 4: Procesoare cu execu\u021bii multiple ale instruc\u021biunilor (<em>Instruction Level Parallelism<\/em>) \u2013 Paragrafele 4.1, 4.2, 4.3, 4.4. \u00cen plus, din acest capitol:<\/li>\r\n<\/ul>\r\n<p style=\"font-weight: 400;\">o\u00a0\u00a0Microprocesoare\u00a0<em>multi-thread<\/em>\u00a0(Par. 4.5b)<\/p>\r\n<p style=\"font-weight: 400;\">o\u00a0Microprocesoare cu<em>\u00a0scheduling<\/em>\u00a0static: Par. 4.6 (optimizare local\u0103 \u2013 metoda\u00a0<em>List Scheduling<\/em>), Par. 4.7 (optimizare global\u0103 \u2013\u00a0<em>Trace Scheduling<\/em>), Par. 4.8 (optimizarea buclelor de program \u2013\u00a0<em>Loop Unrolling<\/em>\u00a0\u0219i\u00a0<em>Software Pipelinining<\/em>), Par. 4.9 (Microarhitecturi\u00a0<em>TTA<\/em>) \u0219i Par. 4.11 (Arhitecturi cu paralelism la nivelul datelor \u2013\u00a0<em>SIMD<\/em>sau vectoriale)<\/p>\r\n<p style=\"font-weight: 400;\">o\u00a0\u00a0\u00a0<em>S<\/em>isteme multiprocesor \u2013 Par. 4.12, f\u0103r\u0103 sub-paragraful intitulat \u201eDirec\u021bii de dezvoltare actuale \u00een sistemele\u00a0<em>multicore \/manycore\u201d<\/em><\/p>\r\n<p style=\"font-weight: 400;\">Ne exprim\u0103m a\u0219adar speran\u021ba c\u0103 aceast\u0103 lucrare, sub forma unui tratat universitar unitar, se va dovedi util\u0103 studen\u021bilor din domeniul \u0219tiin\u021bei \/ ingineriei calculatoarelor \u0219i tehnologiei informa\u021biei sau din domenii conexe (electronic\u0103 \u0219i telecomunica\u021bii, ingineria sistemelor, inginerie electric\u0103 etc.), dar \u0219i speciali\u0219tilor care doresc s\u0103-\u0219i consolideze cuno\u0219tin\u021bele referitoare la bazele arhitecturale ale microprocesoarelor \u0219i sistemelor de calcul moderne (\u0219i nu numai).<\/p>\r\n<p style=\"font-weight: 400;\">\u00cen finalul acestei prefe\u021be, autorul \u00ee\u0219i exprim\u0103 gratitudinea fa\u021b\u0103 de so\u021bia sa, Maria Vin\u021ban, \u0219i fa\u021b\u0103 de fiul s\u0103u, Radu Vin\u021ban, pentru sprijinul generos acordat pe parcursul elabor\u0103rii acestei c\u0103r\u021bi \u0219i nu numai.<\/p>\r\n<p style=\"font-weight: 400;\"><\/p>\r\n<p style=\"font-weight: 400;\"><em>22 iulie 2016, Sibiu<\/em><\/p>\r\n<p style=\"font-weight: 400;\"><em>Lucian N. Vin\u021ban<\/em><\/p>\r\n<p style=\"font-weight: 400;\"><\/p>\r\n<b><strong>CUPRINS<\/strong><\/b>\r\n<ol>\r\n \t<li style=\"font-weight: 400;\"><b><strong> O SCURT\u0102 ISTORIE A SISTEMELOR DE CALCUL<\/strong><\/b>&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;. 16<\/li>\r\n \t<li style=\"font-weight: 400;\"><b><\/b><b><strong>O INTRODUCERE \u00ceN FILOSOFIA MICROSISTEMELOR DE CALCUL<\/strong><\/b>..25<\/li>\r\n<\/ol>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 1.1 SCHEMA BLOC A UNUI MICROSISTEM. ROLUL<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 BLOCURILOR COMPONENTE, FUNC\u0162IONARE DE ANSAMBLU\u00a0&#8230;&#8230;.. 25<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 1.2 MODURI DE LUCRU \u00ceNTRE MICROPROCESOR \u015eI INTERFE\u0162ELE I\/O . 40<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 1.2.1\u00a0MODUL DE LUCRU PRIN INTEROGARE (\u201cPOLLING\u201d)\u00a0&#8230;&#8230;&#8230;&#8230;&#8230;&#8230; 40<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a01.2.2 MODUL DE LUCRU PRIN \u00ceNTRERUPERI HARDWARE &#8230;&#8230;&#8230;&#8230;&#8230;.. 42<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a01.2.3 MODUL DE LUCRU PRIN TRANSFER DMA (DIRECT MEMORY<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ACCESS)\u00a0&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;. 46<\/p>\r\n\r\n<ol start=\"2\">\r\n \t<li style=\"font-weight: 400;\"><b><\/b><b><strong>ARHITECTURA SISTEMULUI IERARHIZAT DE MEMORIE<\/strong><\/b>&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;.. 53<\/li>\r\n<\/ol>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 2.1 MEMORII CACHE&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230; 53<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 2.2 MEMORIA VIRTUAL\u0102 &#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;.. 89<\/p>\r\n\r\n<ol start=\"3\">\r\n \t<li style=\"font-weight: 400;\"><b><\/b><b><strong>PROCESOARE<em>PIPELINE<\/em>\u00a0SCALARE CU SET OPTIMIZAT DE<\/strong><\/b><\/li>\r\n<\/ol>\r\n<p style=\"font-weight: 400;\"><b><strong>\u00a0\u00a0\u00a0\u00a0 INSTRUC\u0162IUNI<\/strong><\/b>\u00a0&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;.. 99<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 3.1.\u00a0MODELUL RISC. GENEZ\u0102 \u015eI CARACTERISTICI GENERALE&#8230;&#8230;&#8230;&#8230;..\u00a099<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 3.2.\u00a0SET DE INSTRUC\u0162IUNI. REGI\u015eTRI INTERNI LA MODELUL<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ARHITECTURAL RISC&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230; 101<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 3.2.1.\u00a0DUALITATEA ARHITECTUR\u0102 \u2013 APLICA\u0162IE: IMPLEMENTAREA<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 GESTIUNII STIVELOR DE DATE ASOCIATE FUNC\u0162IILOR C&#8230;.. 109<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a03.2.2.\u00a0IMPLEMENTAREA RECURSIVIT\u0102\u0162II&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;.. 114<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 3.3.\u00a0ARHITECTURA SISTEMULUI DE MEMORIE LA PROCESOARELE<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 RISC&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230; 116<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 3.4.\u00a0PROCESAREA PIPELINE \u00ceN CADRUL PROCESOARELOR SCALARE\u00a0..118<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 3.4.1.\u00a0DEFINIREA CONCEPTULUI DE ARHITECTUR\u0102 PIPELINE<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 SCALAR\u0102&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230; 119<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 3.4.2.\u00a0PRINCIPIUL DE PROCESARE \u00ceNTR-UN PROCESOR PIPELINE.. 122<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 3.4.3.\u00a0STRUCTURA PRINCIPIAL\u0102 A UNUI PROCESOR RISC&#8230;&#8230;&#8230;&#8230;&#8230;. 125<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 3.4.4.\u00a0PROBLEMA HAZARDURILOR \u00ceN PROCESOARELE RISC&#8230;&#8230;&#8230;. 129<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 3.4.4.1.\u00a0HAZARDURI STRUCTURALE (HS): PROBLEME<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 IMPLICATE \u015eI SOLU\u0162II&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230; 130<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 3.4.4.2.\u00a0HAZARDURI DE DATE: DEFINIRE, CLASIFICARE,<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 SOLU\u0162II DE EVITARE A EFECTELOR DEFAVORABILE&#8230;.. 135<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a03.4.4.3.\u00a0HAZARDURI DE RAMIFICA\u0162IE (HR): PROBLEME<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 IMPLICATE \u015eI SOLU\u0162II&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;\u00a0143<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 3.4.5.\u00a0PROBLEMA EXCEP\u0162IILOR \u00ceN PROCESOARELE RISC&#8230;&#8230;&#8230;&#8230;&#8230;.. 197<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 3.4.6.\u00a0AMBIGUITATEA REFERIN\u0162ELOR LA MEMORIE&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;.. 200<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 3.4.7.\u00a0EXECU\u0162IA CONDI\u0162IONAT\u0102 \u015eI SPECULATIV\u0102&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;. 203<\/p>\r\n\r\n<ol start=\"4\">\r\n \t<li style=\"font-weight: 400;\"><b><\/b><b><strong>PROCESOARE CU EXECU\u0162II MULTIPLE ALE<\/strong><\/b><\/li>\r\n<\/ol>\r\n<p style=\"font-weight: 400;\"><b><strong>INSTRUC\u0162IUNILOR. MULTIPROCESOARE<\/strong><\/b>&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;. 207<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a04.1.\u00a0CONSIDERA\u0162II GENERALE. PROCESOARE SUPERSCALARE<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \u015eI VLIW (EPIC)&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;.. 207<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 4.2.\u00a0MODELE DE PROCESARE \u00ceN ARHITECTURILE SUPERSCALARE&#8230; 228<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 4.3.\u00a0ARHITECTURA LUI R. TOMASULO&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;. 230<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 4.4.\u00a0O ARHITECTUR\u0102 REPREZENTATIV\u0102 DE PROCESOR<\/p>\r\n<p style=\"font-weight: 400;\">SUPERSCALAR&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;. &#8230;239<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 4.5.\u00a0PROBLEME SPECIFICE INSTRUC\u0162IUNILOR DE<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 RAMIFICA\u0162IE \u00ceN ARHITECTURILE CU EXECU\u021aII MULTIPLE&#8230;&#8230;&#8230;. 258<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 4.5.b MICROPROCESOARE MULTI-MICROTHREAD&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230; 260<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 4.6.\u00a0OPTIMIZAREA BASIC-BLOCK-URILOR \u00ceN ARHITECTURILE MEM. 275<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 4.6.1.\u00a0PARTI\u0162IONAREA UNUI PROGRAM \u00ceN &#8222;BASIC-BLOCK&#8221;-URI&#8230;.\u00a0279<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 4.6.2.\u00a0CONSTRUC\u0162IA GRAFULUI DEPENDEN\u0162ELOR DE DATE<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ASOCIAT&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;. 280<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 4.6.3.\u00a0CONCEPTUL C\u0102II CRITICE&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;. 283<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 4.6.4.\u00a0ALGORITMUL &#8222;LIST SCHEDULING&#8221; (LS)&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;. 284<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 4.7.\u00a0PROBLEMA OPTIMIZ\u0102RII GLOBALE \u00ceN CADRUL<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 PROCESOARELOR MEM&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;.. 288<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 4.7.1.\u00a0TEHNICA &#8222;TRACE SCHEDULING&#8221; (TS)&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;.. 289<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 4.8.\u00a0OPTIMIZAREA BUCLELOR DE PROGRAM&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230; 300<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 4.8.1.\u00a0TEHNICA &#8222;LOOP UNROLLING&#8221;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230; 301<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 4.8.2.\u00a0TEHNICA &#8222;SOFTWARE PIPELINING&#8221;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;.. 304<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 4.9.\u00a0ARHITECTURI CU TRANSPORT DECLAN\u015eAT&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230; 307<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 4.10.\u00a0EXTENSII ALE ARHITECTURILOR MEM PE BAZ\u0102 DE<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 REUTILIZARE \u0218I PREDIC\u021aIE A INSTRUC\u021aIUNILOR&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;. 311<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 4.11.\u00a0PROCESAREA VECTORIAL\u0102 (SIMD)&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;.. 349<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 4.12.\u00a0SISTEME MULTIPROCESOR (MIMD)&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230; 363<\/p>\r\n<p style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0 4.13.\u00a0OPTIMIZAREA MULTI-OBIECTIV A SISTEMELOR DE CALCUL&#8230;.. 472<\/p>\r\n\r\n<ol start=\"5\">\r\n \t<li style=\"font-weight: 400;\"><b><strong> PROBLEME PROPUSE SPRE REZOLVARE<\/strong><\/b>&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;. 498<\/li>\r\n<\/ol>\r\n<p style=\"font-weight: 400;\"><b><strong>BIBLIOGRAFIE SELECTIV\u0102<\/strong><\/b>&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;.. 530<\/p>\r\n<p style=\"font-weight: 400;\"><b><strong>GLOSAR DE TERMENI TEHNICI UTILZA\u021aI<\/strong><\/b>&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230; 536<\/p>\r\n<p style=\"font-weight: 400;\">COPERTA A IV-A&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;&#8230;..548<\/p>\r\n<p style=\"font-weight: 400;\"><\/p>","protected":false},"excerpt":{"rendered":"<p>A ap\u0103rut cartea\u00a0Fundamente ale arhitecturii microprocesoarelor,\u00a0autor prof.univ.dr.ing.\u00a0VIN\u0162AN N. LUCIAN,\u00a0Editura Matrix Rom, Bucure\u015fti, ISBN\u00a0978-606-25-0276-8, 2016 (547 pg.) http:\/\/www.matrixrom.ro\/romanian\/editura\/domenii\/cuprins.php?cuprins=FA50 PREFA\u021a\u0102 Scopul principal al acestei c\u0103r\u021bi este acela de a familiariza cititorul cu anumite aspecte, considerate mai importante \u0219i, de asemenea, mai pu\u021bin perisabile, referitoare la arhitectura microprocesoarelor de azi \u0219i, eventual, chiar de m\u00e2ine. A\u0219adar, cartea de [&hellip;]<\/p>\n","protected":false},"author":8,"featured_media":1533,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[87],"tags":[],"class_list":{"0":"post-1532","1":"post","2":"type-post","3":"status-publish","4":"format-standard","5":"has-post-thumbnail","7":"category-carti-publicate-de-catre-membrii-astr"},"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v20.7 (Yoast SEO v27.5) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Fundamente ale arhitecturii microprocesoarelor - astr<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/work.astr.ro\/fundamente-ale-arhitecturii-microprocesoarelor\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Fundamente ale arhitecturii microprocesoarelor\" \/>\n<meta property=\"og:description\" content=\"A ap\u0103rut cartea\u00a0Fundamente ale arhitecturii microprocesoarelor,\u00a0autor prof.univ.dr.ing.\u00a0VIN\u0162AN N. LUCIAN,\u00a0Editura Matrix Rom, Bucure\u015fti, ISBN\u00a0978-606-25-0276-8, 2016 (547 pg.) http:\/\/www.matrixrom.ro\/romanian\/editura\/domenii\/cuprins.php?cuprins=FA50 PREFA\u021a\u0102 Scopul principal al acestei c\u0103r\u021bi este acela de a familiariza cititorul cu anumite aspecte, considerate mai importante \u0219i, de asemenea, mai pu\u021bin perisabile, referitoare la arhitectura microprocesoarelor de azi \u0219i, eventual, chiar de m\u00e2ine. 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